1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a method of forming an oxide liner in a shallow trench isolation structure to improve reliability and reduce the consumption or encroachment of the source/drain or active regions.
2. Description of the Relevant Art
In the fabrication of semiconductor integrated circuits, a plurality of transistors are fabricated into a monolithic substrate. The individual transistors are typically isolated from one another by fabricating various types of silicon dioxide structures between adjacent transistors. In a LOCOS isolation process, the isolation or field regions of the substrate are thermally oxidized to form a relatively thick field oxide structure in the field regions of the substrate. Because the thermal oxidation of silicon is known to consume a portion of the silicon substrate, the LOCOS field oxide extends into the field region of the silicon substrate and provides an isolation material between adjacent active regions of the integrated circuit. The selective oxidation of the field regions in a LOCOS process is achieved by patterning a silicon nitride layer over the active regions of the substrate prior to performing the thermal oxidation step. Although the details of LOCOS processing are familiar to the semiconductor manufacturing industry, LOCOS processing involves drawbacks that make it less than desirable in a variety of advanced processes.
The thermal oxidation process used to fabricate the LOCOS field oxide structure is well known for creating a laterally oriented bird's beak structure that extends into the active regions of the substrate. The consumption of the active regions of the substrate during the LOCOS field oxidation process undesirably consumes regions of the semiconductor substrate that would otherwise be available for active devices such as MOS transistors. It is desirable to fabricate as many transistors into a given area of the substrate as possible to achieve the complex circuits associated with modern VLSI integrated circuits. In addition to the consumption of active regions that occurs during a typical LOCOS field oxidation process, the thermal oxidation process required to achieve a desirable field oxide thickness is typically relatively long in duration. If, for example, a process requires a field oxide with a thickness in excess of approximately 3,000 to 5,000 angstroms, the required thermal oxidation cycle to achieve this thickness is typically in excess of 60 minutes or more. As will be readily appreciated, process steps that require more time are generally undesirable because of the increased cost associated with such processes and the reduced throughput that results from the longer processing times. In addition to the expense and complexity associated with long processing cycles, manufacturers typically try to avoid subjecting a semiconductor wafer to a long thermal process after any impurity distributions have been introduced into the substrate. In many fabrication processes, for example, one or more ion implantation processes have been performed prior to the field oxidation step. These impurity distributions that are present in the substrate prior to the thermal oxidation process will be significantly redistributed during the high temperature processing necessary to generate a sufficient oxide growth rate during the field oxidation step.
For the reasons described, semiconductor manufacturers have sought alternatives to the LOCOS isolation process. In a shallow trench isolation process, a trench is etched into the field regions of the semiconductor substrate and, thereafter, filled with an electrically insulating material to prevent inadvertent coupling of adjacent source/drain regions of neighboring transistors. Although the shallow trench isolation process eliminates the long cycle times and bird's beak formation associated with LOCOS processes, conventional shallow trench isolation processes are not without their drawbacks. It is known that, if the shallow trench isolation dielectric is comprised entirely of a deposited dielectric such as a CVD silicon dioxide formed from a TEOS or silane source, the relatively poor bonding between the deposited dielectric and the surrounding silicon substrate can result in excessive leakage currents and possibly a reduced field threshold voltage. (A field threshold voltage refers to a minimum voltage that must be present above the field isolation structure to generate a channel underneath the isolation structure that forms an unintended conductive path between adjacent source drain regions of neighboring transistors.) It will be appreciated that obtaining the highest possible field threshold voltage is desirable to ensure the highest quality integrated circuit. To improve the interface between the conventional shallow trench isolation process and the surrounding silicon substrate, manufacturers have attempted to line the isolation trench with a thermally formed silicon dioxide. Unfortunately, manufacturers have typically found that, in order to produce a trench liner oxide sufficient to make a significant difference in terms of the liability of the device, the thickness of the liner oxide must be made undesirably large. Thick liner oxides are undesirable in shallow trench isolation processes because the trench liner, like other thermally formed oxides, consumes a portion of the silicon upon which the oxide is grown. In a shallow trench process, the silicon consumed during a liner oxide formation process comprises the active region of the transistor, namely, the source/drain regions. Consistent with the desire to maximize the available active region space and to minimize the amount of silicon real estate dedicated to the isolation structures, it is desirable from a manufacturing perspective to produce isolation dielectric structures with a minimum thickness to minimize the consumption of the active regions.
Even if liner oxides in conventional shallow trench isolation processes were sufficiently thin to address any concerns about the amount of active region consumed by the isolation structures, it is typically difficult to fabricate an isolation structure that adequately prevents migration of mobile impurities within the substrate through the isolation dielectric and possibly settling in an active region of the integrated circuit thereby potentially resulting in the formation of an unwanted impurity distribution within the integrated circuit. Such unwanted impurity distributions can accumulate over the lifetime of the integrated circuit causing undesired effects such as shifts in the threshold voltages of the integrated circuit.
Accordingly, it would be desirable to implement a semiconductor fabrication process in which the manufacturing problems associated with the formation of conventional isolation structures were addressed without significantly increasing the complexity, cost, or manufacturability of the process.